1. Technical Field
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device which performs a refresh operation and a refresh clock signal generator thereof.
2. Discussion of the Related Art
Semiconductor memory devices can generally be categorized as volatile memory devices and nonvolatile memory devices. Volatile memory devices include dynamic random access memory (DRAM) and static random access memory (SRAM), etc. Nonvolatile memory devices include flash memory or read only memory (ROM), etc.
Volatile memory devices are divided into two categories according to whether a recharge operation of data is required. For example, an SRAM cell is generally constructed of a flip-flop circuit and two switches, and data storage can be obtained as long as power is applied. A DRAM cell, on the other hand, includes one capacitor and one transistor. The DRAM cell stores data by accumulating charges in a capacitor; however, data stored in the capacitor disappears after a predetermined time lapses.
To prevent loss of data, data within the DRAM cell is read, and an initial charge must be replenished in conformity with the read information. This operation is repeated periodically to maintain data stored in the DRAM cell. Such a recharge procedure is referred to as a refresh operation.
FIG. 1 is a block diagram illustrating a conventional semiconductor memory device having dynamic memory cells. The semiconductor memory device of FIG. 1 includes a self refresh control signal generator 10, a refresh clock signal generator 12, a refresh address generator 14, a row address decoder 16, and a memory cell array 100.
Functions of the semiconductor memory device of FIG. 1 will be explained below.
The self refresh control signal generator 10 counts a self refresh cycle to generate a self refresh control signal SEF. The refresh clock signal generator 12 is enabled in response to the self refresh control signal SEF to generate a refresh clock signal CLK. The refresh address generator 14 performs a counting operation in response to the refresh clock signal CLK to generate a refresh row address radd. The row address decoder 16 decodes the refresh row address radd to generate a word line enable signal for enabling one of n word lines WL1 to WLn. The memory cell array 100 performs a refresh operation for the memory cells of the word line selected in response to the word line enable signal. Here, the refresh operation reads data of the selected word line via a bit line, then amplifies the data by using a bit line sense amplifier and then writes the data again.
FIG. 2 is a block diagram illustrating a conventional refresh clock signal generator. The refresh clock signal generator of FIG. 2 includes a temperature detector 20 and an oscillator 22.
Functions of the refresh clock signal generator of FIG. 2 will be explained below.
The temperature detector 20 detects an internal temperature, for example, of the semiconductor memory device of FIG. 1, and varies an output voltage Vref according to a temperature variation. The oscillator 22 generates the refresh clock signal CLK whose cycle varies according to the output voltage Vref. The oscillator 22 generates the refresh clock signal CLK with a short cycle in a high temperature section and the refresh clock signal CLK with a long cycle in a low temperature section. In other words, the refresh clock signal CLK with a short cycle is generated when the temperature is high and the refresh clock signal CLK with a lo long cycle is generated when the temperature is low. An example of the refresh clock signal generator of FIG. 2 is disclosed in Korean Patent Publication No. 2002-2659 and its related U.S. Pat. No. 6,597,614, copies of which are incorporated by reference herein in their entirety.
Although the refresh clock signal generator of FIG. 2 can reduce power consumption by varying a self refresh period, the refresh clock signal generator is complicated to design and occupies a large area. Accordingly, there exists a need for a refresh clock signal generator that consumes a small amount of power and that occupies a smaller surface area than a conventional refresh clock signal generator.